Platform · Hardware and models

Verified silicon, targets in bring up, and every recipe we ship.

The same Rust and CUDA source runs on NVIDIA and AMD without a second kernel tree. This page names what is verified, what is in bring up, and every model recipe, generated from the repository at build time.

Who this is forEngineers checking whether their hardware and their models are covered before a pilot.

Verified hardware

GB10 · Blackwell SM121

Verified

NVIDIA DGX Spark

One multi model binary serves a full matrix of hand tuned targets on a single GB10. NVFP4 and FP8, MTP speculative decoding, EP=2 across two DGX Spark units. Every target passes the serve matrix before an image is cut.

Deployment guide ↗

gfx1151 · RDNA 3.5

Runs through SCALE

AMD Strix Halo

One codebase, both vendors. The CUDA kernels compile straight for gfx1151 through SCALE by Spectral Compute. AMD provided the Strix Halo desktop it runs on.

About SCALE ↗

Hopper · SM90

Bring up

NVIDIA H100 and H200

Hopper owned decode and prefill kernels with published receipts in the changelog, bit identical to the reference on the production shapes. Not yet a verified target, and this page will say so until it is.

Blackwell · SM100

Campaign

NVIDIA B200 and GB200

Datacenter Blackwell is the next objective after Hopper, built around the same principle the hardware demonstrates, inference economics improve when the software is designed for the accelerator.

gfx1201 · RDNA 4

In review

AMD Radeon AI PRO R9700

A SCALE target serving Qwen3.8-27B in an open pull request. The compatibility list grows in the open.

Battlemage

In talks

Intel Arc Pro B70

Active conversations with Intel. Nothing is signed and this card will say so until it is.

Models

Every model here has a recipe.

Pick a vendor, then a family. Every card maps to one recipe in the recipe registry, so the site cannot list a model it does not ship.

Qwen3-Coder-Next

Qwen3 Coder Next FP8

fp8 single 80B

metralectl run qwen3-coder-next-fp8

Qwen3-Next

Qwen3 Next 80B A3B NVFP4

nvfp4 single 80B

metralectl run qwen3-next-80b-a3b-nvfp4

Qwen3-VL

Qwen3 VL 30B A3B NVFP4

nvfp4 single 30B

metralectl run qwen3-vl-30b-a3b-nvfp4

Qwen3.5

Qwen3.5 0.8B BF16 Metrale

none single 0.8B

metralectl run qwen3.5-0.8b-bf16-metrale

Qwen3.5 122B A10B NVFP4 EP=2

nvfp4 EP=2 122B

metralectl run qwen3.5-122b-a10b-nvfp4-ep2 --rank 0 --world-size 2 --master-addr <head-node>

Qwen3.5 122B A10B NVFP4 Single

nvfp4 single 122B

metralectl run qwen3.5-122b-a10b-nvfp4-single

Qwen3.5 27B Dense NVFP4

nvfp4 single 27B

metralectl run qwen3.5-27b-dense-nvfp4

Qwen3.5 35B A3B NVFP4

nvfp4 single 35B

metralectl run qwen3.5-35b-a3b-nvfp4

Qwen3.6

Qwen3.6 27B FP8

fp8 single 27B

metralectl run qwen3.6-27b-fp8

Qwen3.6 27B FP8 MTP

fp8 single 27B

metralectl run qwen3.6-27b-fp8-mtp

Qwen3.6 27B NVFP4

nvfp4 single 27B

metralectl run qwen3.6-27b-nvfp4

Qwen3.6 27B NVFP4 Prefill Record

nvfp4 single 27B

metralectl run qwen3.6-27b-nvfp4-prefill-record

Qwen3.6 27B NVFP4 Unsloth

NVFP4 (mixed precision above layer 55) single 27B dense hybrid (48 GDN linear-attn + 16 softmax-attn layers)

metralectl run qwen3.6-27b-nvfp4-unsloth

Qwen3.6 35B A3B FP8 Bf16head

fp8 single 35B

metralectl run qwen3.6-35b-a3b-fp8-bf16head

Qwen3.6 35B A3B FP8 MTP

fp8 single 35B

metralectl run qwen3.6-35b-a3b-fp8-mtp

Qwen3.6 35B A3B FP8 Nvfp4head

fp8 single 35B

metralectl run qwen3.6-35b-a3b-fp8-nvfp4head

Qwen3.6 35B A3B FP8 Nvfp4head Experts NVFP4

fp8 single 35B

metralectl run qwen3.6-35b-a3b-fp8-nvfp4head-experts-nvfp4

Qwen3.6 35B A3B FP8 Nvfp4head Experts NVFP4 Gate Up

fp8 single 35B

metralectl run qwen3.6-35b-a3b-fp8-nvfp4head-experts-nvfp4-gate-up

Qwen3.6 35B A3B NVFP4

nvfp4 single 35B

metralectl run qwen3.6-35b-a3b-nvfp4

Qwen3.6 35B A3B NVFP4 Declared

nvfp4 single 35B

metralectl run qwen3.6-35b-a3b-nvfp4-declared

Qwen3.8

Qwen3.8 27B NVFP4 Dflash2

NVFP4 (compressed-tensors, mixed precision) single

metralectl run qwen3.8-27b-nvfp4-dflash2

Qwen3.8 27B NVFP4 Latency

NVFP4 (compressed-tensors, mixed precision) single

metralectl run qwen3.8-27b-nvfp4-latency

Qwen3.8 27B NVFP4 Throughput

NVFP4 (compressed-tensors, mixed precision) single

metralectl run qwen3.8-27b-nvfp4-throughput

Qwen3.8 27B NVFP4 Unsloth

NVFP4 (mixed precision above layer 55, FP8 linear_attn projections) single 27B dense hybrid (48 GDN linear-attn + 16 softmax-attn layers)

metralectl run qwen3.8-27b-nvfp4-unsloth

Qwen3.8 27B NVFP4 Unsloth Bfcl

NVFP4 (mixed precision above layer 55) single 27B dense hybrid (48 GDN linear-attn + 16 softmax-attn layers)

metralectl run qwen3.8-27b-nvfp4-unsloth-bfcl

Qwen3.8 Flash Next NVFP4

NVFP4 (BF16 n-gram embedding table) single 48 layers (36 GDN linear-attn + 12 full attention), MoE 512 experts top-10

metralectl run qwen3.8-flash-next-nvfp4

Questions

The questions we actually get asked.

Short answers. Each one is backed by something on this site or in the repository.

What hardware does it run on?

NVIDIA DGX Spark (GB10) is verified today, and AMD Strix Halo (gfx1151) runs the same CUDA source compiled through SCALE. Hopper and Blackwell datacenter targets are in active bring up with receipts in the changelog. Expert parallelism across two nodes ships as recipes and a three node topology is being wired up.

Which models can I run?

Every model on this site maps to a recipe in the recipe registry, which is the single source of truth, so the site cannot list a model without one. Qwen leads with the most recipes, alongside Gemma, Nemotron, Mistral, MiniMax and DeepSeek. Bring your own weights and we scope the bring up.

Ask the rest in a working session, or read the deployment guide ↗.

Next step

See it against your own workload.

A side by side ladder on your hardware in week one. Your models, your criteria, your receipt.

Bring us your hardware → Every recipe on GitHub